1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. In particular, it relates to a structure of a device, such as a memory cell, that includes a capacitor contact and a bit contact disposed close to each other in which a short circuit between the contacts is prevented, and a method of manufacturing the same.
2. Related Art
Memory cells used in semiconductor devices, such as DRAM, include a memory cell transistor and a capacitor. As a memory device with high integration density, a Capacitor Over Bit-line (COB) type DRAM has been proposed in which capacitors are disposed in a layer above bit lines.
FIG. 11 is a cross-sectional view of a part of such a COB-type DRAM. Bit contact 12 and capacitor contact 13 are connected to respective cell contacts 11 connected to cell transistors (not shown), and bit line 14 is disposed on bit contact 12. Capacitor contact 13 extends into an upper insulating layer that covers bit line 14 and is connected to a capacitor that includes lower electrode 15, capacitor dielectric film 16 and upper electrode 17.
To prevent a short circuit between a bit line and a capacitor contact, there has been proposed a method of forming a nitride sidewall on the side of the bit line in a self-alignment manner (see Japanese Patent Laid-Open Nos. 2002-231906 and 2003-7854). Alternatively, in Japanese Patent Laid-Open No. 2005-39189, there is proposed a method of preventing a short circuit between a bit line and a capacitor contact by covering both the bit line and the bit contact with a direct nitride film.
On the other hand, based on a different idea, there has been proposed a structure in which a nitride film surrounding an upper part of a bit contact is formed, which is manufactured by partially forming a contact hole for a bit contact, forming a sidewall nitride film on the inner surface of the partially formed contact hole, using the sidewall nitride film as a mask to complete the contact hole having a reduced diameter that extends to the lower structure, filling the contact hole with a conductive material, and planarizing the conductive material by CMP or the like to form the bit contact (Japanese Patent Laid-Open No. 2000-299437).
With the advance of miniaturization of the semiconductor device, the problem of a short circuit between a bit line and a capacitor contact is becoming more serious, and the short-circuit margin between the capacitor contact and the bit contact is decreasing. However, from the viewpoint of ensuring adequate electrical connection, it is not wise to reduce the diameter of the contacts. In addition, considering that alignment is performed on the upper layer, the contacts preferably have larger diameters in upper parts than in lower parts.
Thus, if misalignment of a capacitor contact occurs, the top part of the bit contact, which has the largest diameter, and the capacitor contact are short-circuited. As shown in FIG. 12(a), the top part of bit contact 22 and capacitor contact 23 are in contact with each other and thus short-circuited. FIG. 12(b) is a top view, in which reference numeral 24 denotes a bit line, reference numeral 25 denotes the top surface of bit contact 22, and reference numeral 26 denotes the top surface of capacitor contact 23. FIG. 12(a) is a cross-sectional view taken along the line A-A in FIG. 12(b), in which reference numeral 21 denotes a cell contact. In FIG. 12(a), illustration of the bit line, a capacitor and a cell transistor is omitted.
As disclosed in Japanese Patent Laid-Open No. 2005-39189, a short circuit can be prevented by covering both the bit line and the bit contact with a nitride film. However, to cover the bit contact with a nitride film, the interlayer insulating film covering the bit contact has to be previously removed. Furthermore, in the case of a contact that has a larger diameter in an upper part thereof as shown in FIGS. 12(a) and 12(b), the contact covered with a nitride film is increased in diameter in a lower part thereof, so that there is a possibility that the upper surface of the cell contact in the lower layer that is to be connected to the capacitor contact is partially covered in such a miniaturized structure, and the contact resistance of the capacitor contact increases.
Thus, there is a demand for a structure of a semiconductor device having a miniaturized cell structure or the like in which a short circuit between two contacts that have different heights and are disposed close to each other, such as a bit contact and a capacitor contact, due to a misalignment thereof is prevented without increasing the contact resistance of the capacitor contact.